A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors

por Algredo-Badillo, Ignacio, Morales-Sandoval, Miguel, Medina-Santiago, Alejandro, Hernández-Gracidas, Carlos Arturo, Lobato-Baez, Mariana, Morales-Rosales, Luis Alberto
Publicado 2022

CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions

por Medina-Santiago, Alejandro, Hernández-Gracidas, Carlos Arturo, Morales-Rosales, Luis Alberto, Algredo-Badillo, Ignacio, Amador García, Monica, Orozco Torres, Jorge Antonio
Publicado 2021

An FPGA-based analysis of trade-offs in the presence of ill-conditioning and different precision levels in computations

por Algredo-Badillo, Ignacio, Conde-Mones, José Julio, Hernández-Gracidas, Carlos Arturo, Morín-Castillo, María Monserrat, Oliveros-Oliveros, José Jacobo, Feregrino-Uribe, Claudia
Publicado 2020