Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique

por Vlagkoulis, Vasileios, Sari, Aitzan, Antonopoulos, Georgios, Psarakis, Mihalis, Tavoularis, Antonios, Furano, Gianluca, Boatella-Polo, Cesar, Poivey, Christian, Ferlet-Cavrois, Véronique, Kastriotou, Maria, Martinez, Pablo Fernandez, Alía, Rubén García
Publicado 2022

Single Event Effects Characterization of the Programmable Logic of Xilinx Zynq-7000 FPGA Using Very/Ultra High-Energy Heavy Ions

por Vlagkoulis, Vasileios, Sari, Aitzan, Vrachnis, John, Antonopoulos, Georgios, Segkos, Nikolaos, Psarakis, Mihalis, Tavoularis, Antonios, Furano, Gianluca, Polo, Cesar Boatella, Poivey, Christian, Ferlet-Cavrois, Veronique, Kastriotou, Maria, Fernandez Martinez, Pablo, Garcia Alia, Ruben, Voss, Kay-Obbe, Schuy, Christoph
Publicado 2021