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Introductory VHDL : from simulation to synthesis /

Detalles Bibliográficos
Autor principal: Yalamanchili, Sudhakar
Formato: Libro
Lenguaje:English
Publicado: Upper Saddle River, NJ : Prentice Hall, c2001.
Materias:
Tabla de Contenidos:
  • Introduction
  • Modeling digital systems
  • Simulation vs. synthesis
  • Basic language concepts: simulation
  • Basic language concepts: synthesis
  • Modeling behavior: simulation
  • Modeling behavior: synthesis
  • Modeling structure
  • Sub-programs, packages, and libraries
  • Basic I/O
  • Programming mechanics
  • Identifiers, data types, and operators
  • Appendix A: Synthesis hints: beginner's reference
  • Appendix B: VHDL 1987 vs. 1993
  • Appendix C: Active-HDL tutorial
  • Appendix D: Xilinx foundation express tutorial
  • Appendix E: Synopsys FPGA express tutorial
  • Appendix F: Standard VHDL packages
  • Appendix G: A starting program template.