|
|
|
|
| LEADER |
00000cam a2200000 a 4500 |
| 001 |
ocm55286508 |
| 003 |
UV# |
| 005 |
20220810121000.0 |
| 008 |
160621s2004 maua b 001 0 eng d |
| 010 |
|
|
|a 2004051574
|
| 015 |
|
|
|2 bnb
|
| 020 |
|
|
|a 1402076657
|
| 020 |
|
|
|a 9781402076657
|
| 020 |
|
|
|a 1402080638
|q (Ebook)
|
| 020 |
|
|
|a 9781402080630
|q (Ebook)
|
| 040 |
|
|
|a DLC
|b eng
|c DLC
|d BAKER
|d NLGGC
|d BTCTA
|d YDXCP
|d STF
|d UKM
|d OCLCG
|d IG#
|d OCLCQ
|d UKMGB
|d OCLCQ
|d OCLCF
|d NJI
|d OCLCO
|d OCLCQ
|d UV#
|
| 042 |
|
|
|a pcc
|
| 050 |
0 |
0 |
|a TK7874.55
|b G66 2004
|
| 082 |
0 |
0 |
|a 621.3815
|2 22
|
| 100 |
1 |
|
|a Gopalakrishnan, Prakash
|9 427824
|
| 245 |
1 |
0 |
|a Direct transistor-level layout for digital blocks
|c / Prakash Gopalakrishnan, Rob A. Rutenbar.
|
| 260 |
|
|
|a Boston :
|b Kluwer Academic Publishers,
|c ©2004.
|
| 300 |
|
|
|a vii, 125 páginas :
|b ilustraciones ;
|c 24 cm.
|
| 336 |
|
|
|a text
|b txt
|2 rdacontent
|
| 337 |
|
|
|a unmediated
|b n
|2 rdamedia
|
| 338 |
|
|
|a volume
|b nc
|2 rdacarrier
|
| 504 |
|
|
|a Incluye bibliografía (páginas 115-121) e índice.
|
| 505 |
0 |
|
|a 1. Introduction -- 2. Circuit structure and clustering -- 3. Global placement -- 4. Detailed placement and layout results -- 5. Timing-driven placement -- 6. Conclusions -- Appendix.
|
| 650 |
|
4 |
|9 427827
|a Trazado de circuitos integrados
|
| 650 |
|
7 |
|a Circuitos integrados digitales
|9 354609
|
| 650 |
|
4 |
|a Circuitos de transistores
|9 354606
|
| 700 |
1 |
|
|a Rutenbar, Rob A.,
|d 1957-
|9 427828
|
| 942 |
|
|
|2 lcc
|c LIBRO
|
| 999 |
|
|
|c 299602
|d 299602
|
