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Testing and development of the CMS silicon tracker front-end readout electronics
The Compact Muon Solenoid (CMS) is a general purpose detector that will operate at the CERN Large Hadron Collider (LHC), a particle accelerator designed for the study of new physics at the TeV energy scale. A key component of CMS is the Silicon Tracker, which has ~9.3 million detector channels and i...
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Lenguaje: | eng |
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Imperial Coll.
2006
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1009471 |
Sumario: | The Compact Muon Solenoid (CMS) is a general purpose detector that will operate at the CERN Large Hadron Collider (LHC), a particle accelerator designed for the study of new physics at the TeV energy scale. A key component of CMS is the Silicon Tracker, which has ~9.3 million detector channels and is expected to generate over 70% of the total CMS data volume. The Tracker readout system must process data at a rate that is orders of magnitude higher than in any previous particle physics experiment. On-detector readout is performed by the APV25 front end chip. To ensure a Tracker of the highest quality and efficiency, each APV25 must be rigorously verified; a wafer probing test station has been developed for post production quality assurance. The APV25 contains internal pipelines which buffer event data pending readout. An APV Emulator has been designed to prevent APV25 buffer overflow due to random fluctuations in the Level 1 trigger rate. The first stage of the off-detector readout is performed by the Front End Driver (FED). This interfaces the Tracker to the CMS Data Acquisition system and reduces the enormous volume of data output from the detector to a manageable level through the process of Zero Suppression, which involves identifying strips that contain hit information and discarding the remainder. The FED is an important, highly complex device and it is vital for every board to function correctly. An Acceptance Test has been developed to check the functionality of each FED before it leaves the assembly plant. A FED Tester card has also been produced to enable testing of the FED under realistic CMS conditions. The data integrity of the S-Link connection used to read out the FED has been assessed and an extensive suite of software has been written to verify the performance of the FED hardware and firmware. Finally, an alternative algorithm for Common Mode (CM) subtraction has been implemented in the FED firmware, with support for high occupancy events and non-uniform CM. In addition, a novel algorithm for baseline correction in APV frames has been developed. |
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