Front-end electronics for the readout of CdZnTe sensors

The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing...

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Detalles Bibliográficos
Autores principales: Moraes, D, Nygård, E, Rudge, A
Lenguaje:eng
Publicado: 2006
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1015505
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author Moraes, D
Nygård, E
Rudge, A
author_facet Moraes, D
Nygård, E
Rudge, A
author_sort Moraes, D
collection CERN
description The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.
id cern-1015505
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2006
record_format invenio
spelling cern-10155052019-09-30T06:29:59Zhttp://cds.cern.ch/record/1015505engMoraes, DNygård, ERudge, AFront-end electronics for the readout of CdZnTe sensorsDetectors and Experimental TechniquesThe CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.oai:cds.cern.ch:10155052006
spellingShingle Detectors and Experimental Techniques
Moraes, D
Nygård, E
Rudge, A
Front-end electronics for the readout of CdZnTe sensors
title Front-end electronics for the readout of CdZnTe sensors
title_full Front-end electronics for the readout of CdZnTe sensors
title_fullStr Front-end electronics for the readout of CdZnTe sensors
title_full_unstemmed Front-end electronics for the readout of CdZnTe sensors
title_short Front-end electronics for the readout of CdZnTe sensors
title_sort front-end electronics for the readout of cdznte sensors
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1015505
work_keys_str_mv AT moraesd frontendelectronicsforthereadoutofcdzntesensors
AT nygarde frontendelectronicsforthereadoutofcdzntesensors
AT rudgea frontendelectronicsforthereadoutofcdzntesensors

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