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The Level 0 Pixel Trigger System for the ALICE experiment

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and...

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Detalles Bibliográficos
Autores principales: Aglieri-Rinella, G, Kluge, A, Krivda, M
Lenguaje:eng
Publicado: CERN 2007
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/2/01/P01007
https://dx.doi.org/10.5170/CERN-2007-001.361
http://cds.cern.ch/record/1020485
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author Aglieri-Rinella, G
Kluge, A
Krivda, M
author_facet Aglieri-Rinella, G
Kluge, A
Krivda, M
author_sort Aglieri-Rinella, G
collection CERN
description The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers. Multi-channel G-Link receivers were realized in programmable hardware and tested. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.
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publishDate 2007
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spelling cern-10204852019-09-30T06:29:59Zdoi:10.1088/1748-0221/2/01/P01007doi:10.5170/CERN-2007-001.361http://cds.cern.ch/record/1020485engAglieri-Rinella, GKluge, AKrivda, MThe Level 0 Pixel Trigger System for the ALICE experimentDetectors and Experimental TechniquesThe ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers. Multi-channel G-Link receivers were realized in programmable hardware and tested. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.CERNoai:cds.cern.ch:10204852007
spellingShingle Detectors and Experimental Techniques
Aglieri-Rinella, G
Kluge, A
Krivda, M
The Level 0 Pixel Trigger System for the ALICE experiment
title The Level 0 Pixel Trigger System for the ALICE experiment
title_full The Level 0 Pixel Trigger System for the ALICE experiment
title_fullStr The Level 0 Pixel Trigger System for the ALICE experiment
title_full_unstemmed The Level 0 Pixel Trigger System for the ALICE experiment
title_short The Level 0 Pixel Trigger System for the ALICE experiment
title_sort level 0 pixel trigger system for the alice experiment
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/2/01/P01007
https://dx.doi.org/10.5170/CERN-2007-001.361
http://cds.cern.ch/record/1020485
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