Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms

We show an alternative design approach for signal processing algorithms implemented on FPGAs. Instead of writing VHDL code for implementation and maintaining a C-model for algorithm simulation, we derive both models from one common source, allowing generation of synthesizeable VHDL and cycleand bit-...

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Detalles Bibliográficos
Autores principales: Muecke, Manfred, Szumlak, Tomasz
Lenguaje:eng
Publicado: CERN 2007
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2007-001.492
http://cds.cern.ch/record/1034306
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author Muecke, Manfred
Szumlak, Tomasz
author_facet Muecke, Manfred
Szumlak, Tomasz
author_sort Muecke, Manfred
collection CERN
description We show an alternative design approach for signal processing algorithms implemented on FPGAs. Instead of writing VHDL code for implementation and maintaining a C-model for algorithm simulation, we derive both models from one common source, allowing generation of synthesizeable VHDL and cycleand bit-accurate C-Code. We have tested our approach on the LHCb VELO pre-processing algorithms and report on experiences gained during the course of our work.
id cern-1034306
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2007
publisher CERN
record_format invenio
spelling cern-10343062019-09-30T06:29:59Zdoi:10.5170/CERN-2007-001.492http://cds.cern.ch/record/1034306engMuecke, ManfredSzumlak, TomaszUnified C/VHDL Model Generation of FPGA-based LHCb VELO algorithmsDetectors and Experimental TechniquesWe show an alternative design approach for signal processing algorithms implemented on FPGAs. Instead of writing VHDL code for implementation and maintaining a C-model for algorithm simulation, we derive both models from one common source, allowing generation of synthesizeable VHDL and cycleand bit-accurate C-Code. We have tested our approach on the LHCb VELO pre-processing algorithms and report on experiences gained during the course of our work.CERNoai:cds.cern.ch:10343062007
spellingShingle Detectors and Experimental Techniques
Muecke, Manfred
Szumlak, Tomasz
Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
title Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
title_full Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
title_fullStr Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
title_full_unstemmed Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
title_short Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
title_sort unified c/vhdl model generation of fpga-based lhcb velo algorithms
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2007-001.492
http://cds.cern.ch/record/1034306
work_keys_str_mv AT mueckemanfred unifiedcvhdlmodelgenerationoffpgabasedlhcbveloalgorithms
AT szumlaktomasz unifiedcvhdlmodelgenerationoffpgabasedlhcbveloalgorithms

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