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Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms
We show an alternative design approach for signal processing algorithms implemented on FPGAs. Instead of writing VHDL code for implementation and maintaining a C-model for algorithm simulation, we derive both models from one common source, allowing generation of synthesizeable VHDL and cycleand bit-...
| Autores principales: | , |
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| Lenguaje: | eng |
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CERN
2007
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2007-001.492 http://cds.cern.ch/record/1034306 |