Preamplifier-shaper prototype for the Fast Transition Detector of the Compressed Baryonic Matter (CBM) experiment at FAIR

In this work a preamplifier-shaper prototype for the Fast Transition Detector of the Compressed BaryonicMatter (CBM) experiment at FAIR fabricated using a 0.35 μm CMOS technology will be presented. The ASIC integrates 16 identical Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, two bridged-T filters, Common-Mode FeedBack (CMFB) network and two non-inverting level shifting stages. The circuit is optimized for a detector capacitance Cd of (5-10)pF. Measurement results confirm the noise of 330 e− + 12 e−/pF obtained in simulations for a pulse with a Full Width Half Maximum (FWHM) of 71 ns. The circuit recovers to the baseline within 200 ns. The conversion gain is 12.64 mV/fC. An integral nonlinearity of 0.7% is also achieved. The maximum output swing is 2 V. The power consumption is 16 mW/channel where the main contributors are the input transistor and the level shifting stage with 5.3 mW and 6.6 mW, respectively. The total area of the chip is 12 mm2. Although the circuit was designed for a positive input charge it has in addition the ability of handling negative current pulses of about 85% of the typical charge of 165 fC without any degradation of the signal. The chip was submitted for manufacturing in AMS’s C35B4M3 0.35 micron CMOS technology in October 2005. This circuit has been successfully used in the CBM test-beam at GSI Darmstadt in February 2006.