n-XYTER: A CMOS read-out ASIC for a new generation of high rate multichannel counting mode neutron detectors

For a new generation of 2-D neutron detectors developed in the framework of the EU NMI3 project DETNI [1], the 128-channel frontend chip n-XYTER has been designed. To facilitate the reconstruction of single neutron incidence points, the chip has to provide a spatial coordinate (represented by the channel number), as well as time stamp and amplitude information to match the data of x- and y-coordinates. While the random nature of the input signals calls for self-triggered operation of the chip, on-chip derandomisation and sparsi cation is required to exploit the enormous rate capability of these detectors ( 4 106cm􀀀2s􀀀1). The chosen architecture implements a preampli er driving two shapers with di erent time constants per channel. The faster shaper drives a single-pulse discriminator with subsequent time-walk compensation. The output of this circuit is used to latch a 14-bit time stamp with a 2 ns resolution and to enable a peak detector circuit fed by the slower shaper branch. The analogue output of the peak detector as well as the time stamp are stored in a 4-stage FIFO for derandomisation. The readout of these FIFOs is accomplished by a token-ring based multiplexer working at 32 MHz, which accounts for further derandomisation, sparsi cation and dynamic bandwidth distribution. The chip was submitted for manufacturing in AMS's C35B4M3 0.35µm CMOS technology in June 2006.