A single ended low Noise Rail to Rail CMOS Preamplifier

The CMOS scaling process that is mainly driven by the need to improve digital performance poses critical problems in terms of dynamic range to analog design. Conventional preamplifier-architectures that are considered as optimum design practice have proven useful for many decades. To overcome some of the new constraints a variety of components is available. This increases the number of necessary masks and therefore the cost of circuit fabrication. In order to cope with the constraints of today's low supply voltages a rail to rail charge sensitive preamplifier designed in a 0.13 mum process is presented. A comparison is made of the proposed design with conventional architectures. Design parameters like output swing ability, gain, bandwidth, power consumption and noise performance are investigated. Finally, experimental results from a prototype submission are presented.