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A CMOS 130nm Evaluation digitzer chip for silicon strips readout
A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and...
| Autores principales: | , , , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2007
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2007-007.314 http://cds.cern.ch/record/1091463 |
| _version_ | 1780913781541437440 |
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| author | Da Silva, W David, J Dhellot, M Fougeron, D Genat, J F Hermel, R Huppert, J f Kapusta, F Lebbolo, H Pham, T H Rossel, F Savoy-navarro, A Sefri, R Vilalte |
| author_facet | Da Silva, W David, J Dhellot, M Fougeron, D Genat, J F Hermel, R Huppert, J f Kapusta, F Lebbolo, H Pham, T H Rossel, F Savoy-navarro, A Sefri, R Vilalte |
| author_sort | Da Silva, W |
| collection | CERN |
| description | A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power. |
| id | cern-1091463 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2007 |
| publisher | CERN |
| record_format | invenio |
| spelling | cern-10914632019-09-30T06:29:59Zdoi:10.5170/CERN-2007-007.314http://cds.cern.ch/record/1091463engDa Silva, WDavid, JDhellot, MFougeron, DGenat, J FHermel, RHuppert, J fKapusta, FLebbolo, HPham, T HRossel, FSavoy-navarro, ASefri, RVilalteA CMOS 130nm Evaluation digitzer chip for silicon strips readoutXXA CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.CERNoai:cds.cern.ch:10914632007 |
| spellingShingle | XX Da Silva, W David, J Dhellot, M Fougeron, D Genat, J F Hermel, R Huppert, J f Kapusta, F Lebbolo, H Pham, T H Rossel, F Savoy-navarro, A Sefri, R Vilalte A CMOS 130nm Evaluation digitzer chip for silicon strips readout |
| title | A CMOS 130nm Evaluation digitzer chip for silicon strips readout |
| title_full | A CMOS 130nm Evaluation digitzer chip for silicon strips readout |
| title_fullStr | A CMOS 130nm Evaluation digitzer chip for silicon strips readout |
| title_full_unstemmed | A CMOS 130nm Evaluation digitzer chip for silicon strips readout |
| title_short | A CMOS 130nm Evaluation digitzer chip for silicon strips readout |
| title_sort | cmos 130nm evaluation digitzer chip for silicon strips readout |
| topic | XX |
| url | https://dx.doi.org/10.5170/CERN-2007-007.314 http://cds.cern.ch/record/1091463 |
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