A CMOS 130nm Evaluation digitzer chip for silicon strips readout

A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and...

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Detalles Bibliográficos
Autores principales: Da Silva, W, David, J, Dhellot, M, Fougeron, D, Genat, J F, Hermel, R, Huppert, J f, Kapusta, F, Lebbolo, H, Pham, T H, Rossel, F, Savoy-navarro, A, Sefri, R, Vilalte
Lenguaje:eng
Publicado: CERN 2007
Materias:
XX
Acceso en línea:https://dx.doi.org/10.5170/CERN-2007-007.314
http://cds.cern.ch/record/1091463

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