Design of on-chip data sparsification for a mixed-mode MAPS device

The device described in the paper is built up of a bidimensional matrix of Monolithic Active Pixel Sensor (MAPS) and an off-pixel digital readout sparsification circuit. The readout logic is based on std-cells and implements an optimised technique aimed at overcoming the readout speed limit of futur...

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Detalles Bibliográficos
Autor principal: Gabrielli, Alessandro
Lenguaje:eng
Publicado: CERN 2007
Materias:
Accelerators and Storage Rings
Acceso en línea:https://dx.doi.org/10.5170/CERN-2007-007.443
http://cds.cern.ch/record/1091519
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author Gabrielli, Alessandro
author_facet Gabrielli, Alessandro
author_sort Gabrielli, Alessandro
collection CERN
description The device described in the paper is built up of a bidimensional matrix of Monolithic Active Pixel Sensor (MAPS) and an off-pixel digital readout sparsification circuit. The readout logic is based on std-cells and implements an optimised technique aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future HEP experiments. In particular, the readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers in vertex detectors. The work extends a first version of a mixed mode device submitted on Nov. 2006 and implemented with the same technology.
id cern-1091519
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2007
publisher CERN
record_format invenio
spelling cern-10915192019-09-30T06:29:59Zdoi:10.5170/CERN-2007-007.443http://cds.cern.ch/record/1091519engGabrielli, AlessandroDesign of on-chip data sparsification for a mixed-mode MAPS deviceAccelerators and Storage RingsThe device described in the paper is built up of a bidimensional matrix of Monolithic Active Pixel Sensor (MAPS) and an off-pixel digital readout sparsification circuit. The readout logic is based on std-cells and implements an optimised technique aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future HEP experiments. In particular, the readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers in vertex detectors. The work extends a first version of a mixed mode device submitted on Nov. 2006 and implemented with the same technology.CERNoai:cds.cern.ch:10915192007
spellingShingle Accelerators and Storage Rings
Gabrielli, Alessandro
Design of on-chip data sparsification for a mixed-mode MAPS device
title Design of on-chip data sparsification for a mixed-mode MAPS device
title_full Design of on-chip data sparsification for a mixed-mode MAPS device
title_fullStr Design of on-chip data sparsification for a mixed-mode MAPS device
title_full_unstemmed Design of on-chip data sparsification for a mixed-mode MAPS device
title_short Design of on-chip data sparsification for a mixed-mode MAPS device
title_sort design of on-chip data sparsification for a mixed-mode maps device
topic Accelerators and Storage Rings
url https://dx.doi.org/10.5170/CERN-2007-007.443
http://cds.cern.ch/record/1091519
work_keys_str_mv AT gabriellialessandro designofonchipdatasparsificationforamixedmodemapsdevice

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