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Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog
| Autor principal: | |
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| Lenguaje: | eng |
| Publicado: |
Springer
2001
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1137930 |
| _version_ | 1780915465603776512 |
|---|---|
| author | Bening, L |
| author_facet | Bening, L |
| author_sort | Bening, L |
| collection | CERN |
| id | cern-1137930 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2001 |
| publisher | Springer |
| record_format | invenio |
| spelling | cern-11379302021-04-22T01:43:38Zhttp://cds.cern.ch/record/1137930engBening, LPrinciples of verifiable RTL design: a functioning coding style supporting verification processes in verilogComputing and ComputersSpringeroai:cds.cern.ch:11379302001 |
| spellingShingle | Computing and Computers Bening, L Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog |
| title | Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog |
| title_full | Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog |
| title_fullStr | Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog |
| title_full_unstemmed | Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog |
| title_short | Principles of verifiable RTL design: a functioning coding style supporting verification processes in verilog |
| title_sort | principles of verifiable rtl design: a functioning coding style supporting verification processes in verilog |
| topic | Computing and Computers |
| url | http://cds.cern.ch/record/1137930 |
| work_keys_str_mv | AT beningl principlesofverifiablertldesignafunctioningcodingstylesupportingverificationprocessesinverilog |