Digital signal integrity and stability in the ATLAS Level-1 Calorimeter Trigger

The ATLAS Level-1 calorimeter trigger is a hardware-based system with the goal of identifying high-pT objects and to measure total and missing ET in the ATLAS calorimeters within an overall latency of 2.5 microseconds. This trigger system is composed of the Preprocessor which digitises about 7200 an...

Descripción completa

Detalles Bibliográficos
Autores principales: Achenbach, R, Adragna, P, Aharrouche, M, Andrei, V, Åsman, B, Barnett, B M, Bauss, B, Bendel, M, Bohm, C, Booth, J R A, Bracinik, J, Brawn, I P, Charlton, D G, Childers, J T, Collins, N J, Curtis, C J, Davis, A O, Eckweiler, S, Eisenhandler, E F, Faulkner, P J W, Fleckner, J, Föhlisch, F, Gee, C N P, Gillman, A R, Goringer, C, Groll, M, Hadley, D R, Hanke, P, Hellman, S, Hidvegi, A, Hillier, S J, Johansen, M, Kluge, E E, Kühl, T, Landon, M, Lendermann, V, Lilley, J N, Mahboubi, K, Mahout, G, Meier, K, Middleton, R P, Moa, T, Morris, J D, Müller, F, Neusiedl, A, Ohm, C, Oltmann, B, Perera, V J O, Prieur, D P F, Qian, W, Rieke, S, Rühr, F, Sankey, D P C, Schäfer, U, Schmitt, K, Schultz-Coulon, H C, Silverstein, S, Sjölin, J, Staley, R J, Stamen, R, Stockton, M C, Tan, C L A, Tapprogge, S, Thomas, J P, Thompson, P D, Watkins, P M, Watson, A, Weber, P, Wessels, M, Wildt, M
Lenguaje:eng
Publicado: CERN 2008
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2008-008.143
http://cds.cern.ch/record/1138901
Descripción
Sumario:The ATLAS Level-1 calorimeter trigger is a hardware-based system with the goal of identifying high-pT objects and to measure total and missing ET in the ATLAS calorimeters within an overall latency of 2.5 microseconds. This trigger system is composed of the Preprocessor which digitises about 7200 analogue input channels and two digital processors to identify high-pT signatures and to calculate the energy sums. The digital part consists of multi-stage, pipelined custom-built modules. The high demands on connectivity between the initial analogue stage and digital part and between the custom-built modules are presented. Furthermore the techniques to establish timing regimes and verify connectivity and stable operation of these digital links will be described.

Ejemplares similares