Timing and Fast Control and Readout Electronics Aspects of the LHCb Upgrade

LHCb is considering an upgrade towards a full 40 MHz readout [1], possibly in several stages implying that a rudimentary rate control will still be needed. The rate control could be achieved by either maintaining the current L0 trigger infrastructure since it is already operating at 40MHz, or implementing simple local trigger decisions units in the new Readout Boards and control the rate via an 'intelligent' throttle mechanism. In this paper we make a first investigation of the possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We examine the current TFC, define the requirements for a new TFC, and propose a TFC architecture based on a single new Readout Supervisor 'Super-ODIN' instantiating several TFC masters to allow partitioning, and based on a shared high-speed optical link network for both the distribution of timing and synchronous control information, as well as trigger/throttle communication. The TFC interface to the new Readout Boards consists of a bidirectional interface board 'Super-THOR' in each crate which communicates with the Readout Boards through high-speed short distance copper links on either hi-cat cables or a backplane. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver development to make the Readout Boards the TFC and the Experiment Con trol System interface to the Front-End on a subset of the links. Recognizing the expanse of the upgrade, the new TFC architecture allows hybrid operation with the old and new readout electronics. At the end we also outline the necessary R&D studies we intend to undertake.