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The ABCN front-end chip for ATLAS Inner Detector Upgrade

We present the design of the ABCN front-end chip implemented in a CMOS 0.25 μm technology and optimized for short silicon strip detectors as foreseen for the ATLAS Silicon Tracker Upgrade. A primary aim of this project is to develop an ASIC with full functionality required for readout of short silic...

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Autor principal: Kaplon, J
Lenguaje:eng
Publicado: CERN 2008
Materias:
Acceso en línea:https://dx.doi.org/10.5170/CERN-2008-008.116
http://cds.cern.ch/record/1158514
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author Kaplon, J
author_facet Kaplon, J
author_sort Kaplon, J
collection CERN
description We present the design of the ABCN front-end chip implemented in a CMOS 0.25 μm technology and optimized for short silicon strip detectors as foreseen for the ATLAS Silicon Tracker Upgrade. A primary aim of this project is to develop an ASIC with full functionality required for readout of short silicon strips in the SLHC environment in a cost-effective and proven technology. Design efforts have been focused on optimizing noise and power performance of the front-end circuit for low detector capacitance, minimizing power consumption in digital blocks and on compatibility with new power distribution schemes being developed for future tracker detectors. The architecture of the chip as well as critical and novel design aspects are discussed in the paper. The ABCN ASIC will serve as a basic test vehicle in an extensive program on development of sensors and modules for the ATLAS Silicon Tracker Upgrade.
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institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2008
publisher CERN
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spelling cern-11585142019-09-30T06:29:59Zdoi:10.5170/CERN-2008-008.116http://cds.cern.ch/record/1158514engKaplon, JThe ABCN front-end chip for ATLAS Inner Detector UpgradeDetectors and Experimental TechniquesWe present the design of the ABCN front-end chip implemented in a CMOS 0.25 μm technology and optimized for short silicon strip detectors as foreseen for the ATLAS Silicon Tracker Upgrade. A primary aim of this project is to develop an ASIC with full functionality required for readout of short silicon strips in the SLHC environment in a cost-effective and proven technology. Design efforts have been focused on optimizing noise and power performance of the front-end circuit for low detector capacitance, minimizing power consumption in digital blocks and on compatibility with new power distribution schemes being developed for future tracker detectors. The architecture of the chip as well as critical and novel design aspects are discussed in the paper. The ABCN ASIC will serve as a basic test vehicle in an extensive program on development of sensors and modules for the ATLAS Silicon Tracker Upgrade.CERNoai:cds.cern.ch:11585142008
spellingShingle Detectors and Experimental Techniques
Kaplon, J
The ABCN front-end chip for ATLAS Inner Detector Upgrade
title The ABCN front-end chip for ATLAS Inner Detector Upgrade
title_full The ABCN front-end chip for ATLAS Inner Detector Upgrade
title_fullStr The ABCN front-end chip for ATLAS Inner Detector Upgrade
title_full_unstemmed The ABCN front-end chip for ATLAS Inner Detector Upgrade
title_short The ABCN front-end chip for ATLAS Inner Detector Upgrade
title_sort abcn front-end chip for atlas inner detector upgrade
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2008-008.116
http://cds.cern.ch/record/1158514
work_keys_str_mv AT kaplonj theabcnfrontendchipforatlasinnerdetectorupgrade
AT kaplonj abcnfrontendchipforatlasinnerdetectorupgrade