Readout architecture of the ATLAS upgraded tracker

The basic concept of the Inner Detector in the Atlas Detector upgraded for the Super-LHC is being elaborated and proposed. The readout electronics of this new detector is based on a hierarchical architecture involving front-end chips (FEIC), Module Controller chips (MC) and Stave Controller chips (SC) and a few high speed readout links. The design is still in a very early phase and a lot needs more detailed studies, however, some architectural issues can already be described. This article will briefly describe the proposed detector layout and its environmental conditions, the proposed readout architecture and the main parameters associated to it (mainly for the strip detector), the different options for the detector control system and the powering of the readout electronics.