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Readout architecture of the ATLAS upgraded tracker

The basic concept of the Inner Detector in the Atlas Detector upgraded for the Super-LHC is being elaborated and proposed. The readout electronics of this new detector is based on a hierarchical architecture involving front-end chips (FEIC), Module Controller chips (MC) and Stave Controller chips (S...

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Detalles Bibliográficos
Autores principales:	Darbo, G, Farthouat, P, Grillo, A
Lenguaje:	eng
Publicado:	CERN 2008
Materias:	Detectors and Experimental Techniques
Acceso en línea:	https://dx.doi.org/10.5170/CERN-2008-008.349 http://cds.cern.ch/record/1158658

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