High-Resolution Time-to-Digital Converter in Field Programmable Gate Array

Two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to tes...

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Detalles Bibliográficos
Autores principales: Aloisio, A, Branchini, P, Cicalese, R, Giordano, R, Izzo, V, Loffredo, S, Lomoro, R
Lenguaje:eng
Publicado: CERN 2008
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2008-008.383
http://cds.cern.ch/record/1158663
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author Aloisio, A
Branchini, P
Cicalese, R
Giordano, R
Izzo, V
Loffredo, S
Lomoro, R
author_facet Aloisio, A
Branchini, P
Cicalese, R
Giordano, R
Izzo, V
Loffredo, S
Lomoro, R
author_sort Aloisio, A
collection CERN
description Two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.
id cern-1158663
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2008
publisher CERN
record_format invenio
spelling cern-11586632019-09-30T06:29:59Zdoi:10.5170/CERN-2008-008.383http://cds.cern.ch/record/1158663engAloisio, ABranchini, PCicalese, RGiordano, RIzzo, VLoffredo, SLomoro, RHigh-Resolution Time-to-Digital Converter in Field Programmable Gate ArrayDetectors and Experimental TechniquesTwo high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.CERNoai:cds.cern.ch:11586632008
spellingShingle Detectors and Experimental Techniques
Aloisio, A
Branchini, P
Cicalese, R
Giordano, R
Izzo, V
Loffredo, S
Lomoro, R
High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
title High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
title_full High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
title_fullStr High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
title_full_unstemmed High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
title_short High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
title_sort high-resolution time-to-digital converter in field programmable gate array
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2008-008.383
http://cds.cern.ch/record/1158663
work_keys_str_mv AT aloisioa highresolutiontimetodigitalconverterinfieldprogrammablegatearray
AT branchinip highresolutiontimetodigitalconverterinfieldprogrammablegatearray
AT cicaleser highresolutiontimetodigitalconverterinfieldprogrammablegatearray
AT giordanor highresolutiontimetodigitalconverterinfieldprogrammablegatearray
AT izzov highresolutiontimetodigitalconverterinfieldprogrammablegatearray
AT loffredos highresolutiontimetodigitalconverterinfieldprogrammablegatearray
AT lomoror highresolutiontimetodigitalconverterinfieldprogrammablegatearray

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