Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST

fastest block transfer cycle offered by the VME64x standard. The maximum achievable data-rate foreseen by the protocol is 320 MByte/s. In this paper we present a reference design based on a FPGA, for the reader willing to implement 2eSST in his VME64x application. By using this template, we have des...

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Detalles Bibliográficos
Autores principales: Aloisio, A, Capasso, L, Giordano, R, Izzo, V
Lenguaje:eng
Publicado: CERN 2008
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2008-008.454
http://cds.cern.ch/record/1159545
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author Aloisio, A
Capasso, L
Giordano, R
Izzo, V
author_facet Aloisio, A
Capasso, L
Giordano, R
Izzo, V
author_sort Aloisio, A
collection CERN
description fastest block transfer cycle offered by the VME64x standard. The maximum achievable data-rate foreseen by the protocol is 320 MByte/s. In this paper we present a reference design based on a FPGA, for the reader willing to implement 2eSST in his VME64x application. By using this template, we have designed a custom Bit Error Rate Tester, in order to probe the block transfer reliability within and beyond the data rate limit presently set by the standard. Our results show that 800 MByte/s data transfers can be achieved in a 21 slots crate with a BER smaller than 10−12.
id cern-1159545
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2008
publisher CERN
record_format invenio
spelling cern-11595452019-09-30T06:29:59Zdoi:10.5170/CERN-2008-008.454http://cds.cern.ch/record/1159545engAloisio, ACapasso, LGiordano, RIzzo, VAchieving Best Performance with VME-based Data Acquisition Systems and 2eSSTDetectors and Experimental Techniquesfastest block transfer cycle offered by the VME64x standard. The maximum achievable data-rate foreseen by the protocol is 320 MByte/s. In this paper we present a reference design based on a FPGA, for the reader willing to implement 2eSST in his VME64x application. By using this template, we have designed a custom Bit Error Rate Tester, in order to probe the block transfer reliability within and beyond the data rate limit presently set by the standard. Our results show that 800 MByte/s data transfers can be achieved in a 21 slots crate with a BER smaller than 10−12.CERNoai:cds.cern.ch:11595452008
spellingShingle Detectors and Experimental Techniques
Aloisio, A
Capasso, L
Giordano, R
Izzo, V
Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
title Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
title_full Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
title_fullStr Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
title_full_unstemmed Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
title_short Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
title_sort achieving best performance with vme-based data acquisition systems and 2esst
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2008-008.454
http://cds.cern.ch/record/1159545
work_keys_str_mv AT aloisioa achievingbestperformancewithvmebaseddataacquisitionsystemsand2esst
AT capassol achievingbestperformancewithvmebaseddataacquisitionsystemsand2esst
AT giordanor achievingbestperformancewithvmebaseddataacquisitionsystemsand2esst
AT izzov achievingbestperformancewithvmebaseddataacquisitionsystemsand2esst

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