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Achieving Best Performance with VME-based Data Acquisition Systems and 2eSST
fastest block transfer cycle offered by the VME64x standard. The maximum achievable data-rate foreseen by the protocol is 320 MByte/s. In this paper we present a reference design based on a FPGA, for the reader willing to implement 2eSST in his VME64x application. By using this template, we have des...
| Autores principales: | , , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2008
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2008-008.454 http://cds.cern.ch/record/1159545 |