The ALICE Level 0 Pixel Trigger Driver Layer

The ALICE Silicon Pixel Detector (SPD) includes 120 detector modules each containing 10 pixel chips. Each pixel chip is capable of generating a FastOR signal indicating the presence of at least one pixel hit in the corresponding 8192 pixel matrix. The Pixel Trigger (PIT) System has been implemented to process the 1200 Fast-Or signals from the SPD and to provide an input signal to the ALICE Central Trigger Processor (CTP) for the fastest (Level 0) trigger decision within a latency of 800 ns. Working as a decision criteria for ALICE, the data flow need to be monitored carefully and status information needs to be made available. Therefore the PIT control system required an accurate design of hardware and software solutions to implement a coordinated operation of the PIT and the ALICE systems to which it interfaces. A driver layer was developed under stringent requirements of robustness and reusability. It qualifies as a general purpose hardware driver for electronic systems. It uses the ALICE Digital Data Link (DDL) front end board (SIU) to communicate with the PIT hardware. We present here the design, and the implementation of the Pixel Trigger Front End Device (FED) Server .