An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger

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The ATLAS Level-1 Muon trigger is built as a synchronous pipeline and includes some high-speed serial links in order to transfer data from the detector to the counting room. The links are based on the GLink chip-set, which performs transfers data with a fixed latency. Despite this unique timing feat...

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Autores principales: Aloisio, A, Cevenini, F, Giordano, R, Izzo, V
Lenguaje:eng
Publicado: 2009
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1207117
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author Aloisio, A
Cevenini, F
Giordano, R
Izzo, V
author_facet Aloisio, A
Cevenini, F
Giordano, R
Izzo, V
author_sort Aloisio, A
collection CERN
description The ATLAS Level-1 Muon trigger is built as a synchronous pipeline and includes some high-speed serial links in order to transfer data from the detector to the counting room. The links are based on the GLink chip-set, which performs transfers data with a fixed latency. Despite this unique timing feature, the production discontinued and no compatible off-the-shelf chip-sets are available. A replacement for the receivers in the counting room in case of failures is needed. We developed a replacement solution for G-Link transmitters and receivers, based on the gigabit serial IO (GTP) embedded in a Xilinx Virtex5-LXT Field Programmable Gate Array (FPGA).
id cern-1207117
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
record_format invenio
spelling cern-12071172019-09-30T06:29:59Zhttp://cds.cern.ch/record/1207117engAloisio, ACevenini, FGiordano, RIzzo, VAn FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon TriggerDetectors and Experimental TechniquesThe ATLAS Level-1 Muon trigger is built as a synchronous pipeline and includes some high-speed serial links in order to transfer data from the detector to the counting room. The links are based on the GLink chip-set, which performs transfers data with a fixed latency. Despite this unique timing feature, the production discontinued and no compatible off-the-shelf chip-sets are available. A replacement for the receivers in the counting room in case of failures is needed. We developed a replacement solution for G-Link transmitters and receivers, based on the gigabit serial IO (GTP) embedded in a Xilinx Virtex5-LXT Field Programmable Gate Array (FPGA).ATL-DAQ-SLIDE-2009-269oai:cds.cern.ch:12071172009-09-17
spellingShingle Detectors and Experimental Techniques
Aloisio, A
Cevenini, F
Giordano, R
Izzo, V
An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger
title An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger
title_full An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger
title_fullStr An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger
title_full_unstemmed An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger
title_short An FPGA-based Emulation of the G-Link chip-set for the ATLAS Level-1 Barrel Muon Trigger
title_sort fpga-based emulation of the g-link chip-set for the atlas level-1 barrel muon trigger
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1207117
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