A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN

LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on bidirectional high-speed optical links using the latest FPGA transceivers. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver to make the Readout Boards the TFC and the Control System interface to the Front-End