A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN

LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allow...

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Detalles Bibliográficos
Autores principales: Alessio, F, Jacobsson, R, Guzik, Z
Lenguaje:eng
Publicado: 2009
Acceso en línea:http://cds.cern.ch/record/1209646
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author Alessio, F
Jacobsson, R
Guzik, Z
author_facet Alessio, F
Jacobsson, R
Guzik, Z
author_sort Alessio, F
collection CERN
description LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on bidirectional high-speed optical links using the latest FPGA transceivers. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver to make the Readout Boards the TFC and the Control System interface to the Front-End
id cern-1209646
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
record_format invenio
spelling cern-12096462019-09-30T06:29:59Zhttp://cds.cern.ch/record/1209646engAlessio, FJacobsson, RGuzik, ZA 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERNLHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on bidirectional high-speed optical links using the latest FPGA transceivers. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver to make the Readout Boards the TFC and the Control System interface to the Front-EndPoster-2009-128oai:cds.cern.ch:12096462009-09-21
spellingShingle Alessio, F
Jacobsson, R
Guzik, Z
A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN
title A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN
title_full A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN
title_fullStr A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN
title_full_unstemmed A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN
title_short A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN
title_sort 40 mhz trigger-free readout architecture for the lhcb experiment at cern
url http://cds.cern.ch/record/1209646
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