FE-I4, the New ATLAS Pixel Chip for Upgraded LHC Luminosities

The new ATLAS pixel chip FE-I4 is being developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC. FE-I4 is designed in a 130 nm technology and is based on an array of 80 by 336 pixels, each 50×250 μm2 and consisting of analog and digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides an elegant solution to the problem of timewalk. The chip periphery contains a control block, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b coder and a clock multiplier unit, which handles data transmission up to 160 Mb/s for the IBL.