Reduction techniques of the back gate effect in the SOI Pixel Detector

We have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer als...

Descripción completa

Detalles Bibliográficos
Autores principales: Ichimiya, R, Arai, Y, Fukuda, K, Kurachi, I, Kuriyama, N, Ohno, M, Okihara, M
Lenguaje:eng
Publicado: CERN 2009
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.68
http://cds.cern.ch/record/1234869
_version_ 1780918524740370432
author Ichimiya, R
Arai, Y
Fukuda, K
Kurachi, I
Kuriyama, N
Ohno, M
Okihara, M
author_facet Ichimiya, R
Arai, Y
Fukuda, K
Kurachi, I
Kuriyama, N
Ohno, M
Okihara, M
author_sort Ichimiya, R
collection CERN
description We have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer also affects the transistor operation in the adjacent circuit layer. This limits the applicable sensor bias well below the full depletion voltage. To overcome this, we performed a TCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results are presented.
id cern-1234869
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
record_format invenio
spelling cern-12348692019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.68http://cds.cern.ch/record/1234869engIchimiya, RArai, YFukuda, KKurachi, IKuriyama, NOhno, MOkihara, MReduction techniques of the back gate effect in the SOI Pixel DetectorDetectors and Experimental TechniquesWe have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer also affects the transistor operation in the adjacent circuit layer. This limits the applicable sensor bias well below the full depletion voltage. To overcome this, we performed a TCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results are presented.CERNoai:cds.cern.ch:12348692009
spellingShingle Detectors and Experimental Techniques
Ichimiya, R
Arai, Y
Fukuda, K
Kurachi, I
Kuriyama, N
Ohno, M
Okihara, M
Reduction techniques of the back gate effect in the SOI Pixel Detector
title Reduction techniques of the back gate effect in the SOI Pixel Detector
title_full Reduction techniques of the back gate effect in the SOI Pixel Detector
title_fullStr Reduction techniques of the back gate effect in the SOI Pixel Detector
title_full_unstemmed Reduction techniques of the back gate effect in the SOI Pixel Detector
title_short Reduction techniques of the back gate effect in the SOI Pixel Detector
title_sort reduction techniques of the back gate effect in the soi pixel detector
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2009-006.68
http://cds.cern.ch/record/1234869
work_keys_str_mv AT ichimiyar reductiontechniquesofthebackgateeffectinthesoipixeldetector
AT araiy reductiontechniquesofthebackgateeffectinthesoipixeldetector
AT fukudak reductiontechniquesofthebackgateeffectinthesoipixeldetector
AT kurachii reductiontechniquesofthebackgateeffectinthesoipixeldetector
AT kuriyaman reductiontechniquesofthebackgateeffectinthesoipixeldetector
AT ohnom reductiontechniquesofthebackgateeffectinthesoipixeldetector
AT okiharam reductiontechniquesofthebackgateeffectinthesoipixeldetector

Ejemplares similares