Low Power Analog Design in Scaled Technologies

In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some d...

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Detalles Bibliográficos
Autores principales: Baschirotto, A, Chironi, V, Cocciolo, G, D’Amico, S, De Matteis, M, Delizia, P
Lenguaje:eng
Publicado: CERN 2009
Materias:
Engineering
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.103
http://cds.cern.ch/record/1234878
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author Baschirotto, A
Chironi, V
Cocciolo, G
D’Amico, S
De Matteis, M
Delizia, P
author_facet Baschirotto, A
Chironi, V
Cocciolo, G
D’Amico, S
De Matteis, M
Delizia, P
author_sort Baschirotto, A
collection CERN
description In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.
id cern-1234878
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
record_format invenio
spelling cern-12348782019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.103http://cds.cern.ch/record/1234878engBaschirotto, AChironi, VCocciolo, GD’Amico, SDe Matteis, MDelizia, PLow Power Analog Design in Scaled TechnologiesEngineeringIn this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.CERNoai:cds.cern.ch:12348782009
spellingShingle Engineering
Baschirotto, A
Chironi, V
Cocciolo, G
D’Amico, S
De Matteis, M
Delizia, P
Low Power Analog Design in Scaled Technologies
title Low Power Analog Design in Scaled Technologies
title_full Low Power Analog Design in Scaled Technologies
title_fullStr Low Power Analog Design in Scaled Technologies
title_full_unstemmed Low Power Analog Design in Scaled Technologies
title_short Low Power Analog Design in Scaled Technologies
title_sort low power analog design in scaled technologies
topic Engineering
url https://dx.doi.org/10.5170/CERN-2009-006.103
http://cds.cern.ch/record/1234878
work_keys_str_mv AT baschirottoa lowpoweranalogdesigninscaledtechnologies
AT chironiv lowpoweranalogdesigninscaledtechnologies
AT cocciolog lowpoweranalogdesigninscaledtechnologies
AT damicos lowpoweranalogdesigninscaledtechnologies
AT dematteism lowpoweranalogdesigninscaledtechnologies
AT deliziap lowpoweranalogdesigninscaledtechnologies

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