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Low Power Analog Design in Scaled Technologies
In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some d...
| Autores principales: | , , , , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2009
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.103 http://cds.cern.ch/record/1234878 |