Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a...

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Detalles Bibliográficos
Autores principales: Gallin-Martel, L, Dzahini, D, Hostachy, J Y, Rarbi, F, Rossetto, O
Lenguaje:eng
Publicado: CERN 2009
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.127
http://cds.cern.ch/record/1234882
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author Gallin-Martel, L
Dzahini, D
Hostachy, J Y
Rarbi, F
Rossetto, O
author_facet Gallin-Martel, L
Dzahini, D
Hostachy, J Y
Rarbi, F
Rossetto, O
author_sort Gallin-Martel, L
collection CERN
description The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.
id cern-1234882
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
record_format invenio
spelling cern-12348822019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.127http://cds.cern.ch/record/1234882engGallin-Martel, LDzahini, DHostachy, J YRarbi, FRossetto, ODesign of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronicsDetectors and Experimental TechniquesThe ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.CERNoai:cds.cern.ch:12348822009
spellingShingle Detectors and Experimental Techniques
Gallin-Martel, L
Dzahini, D
Hostachy, J Y
Rarbi, F
Rossetto, O
Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics
title Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics
title_full Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics
title_fullStr Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics
title_full_unstemmed Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics
title_short Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics
title_sort design of high dynamic range digital to analog converters for the calibration of the calice si-w ecal readout electronics
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2009-006.127
http://cds.cern.ch/record/1234882
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