Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector

A prototype readout system has been developed for the future Belle-II Silicon Vertex Detector at the Super-KEK-B factory in Tsukuba, Japan. It will receive raw data from double-sided sensors with a total of approximately 240,000 strips read out by APV25 chips at a trigger rate of up to 30kHz and per...

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Detalles Bibliográficos
Autores principales: Friedl, M, Irmler, C, Pernicka, M
Lenguaje:eng
Publicado: CERN 2009
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.417
http://cds.cern.ch/record/1235848
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author Friedl, M
Irmler, C
Pernicka, M
author_facet Friedl, M
Irmler, C
Pernicka, M
author_sort Friedl, M
collection CERN
description A prototype readout system has been developed for the future Belle-II Silicon Vertex Detector at the Super-KEK-B factory in Tsukuba, Japan. It will receive raw data from double-sided sensors with a total of approximately 240,000 strips read out by APV25 chips at a trigger rate of up to 30kHz and perform strip reordering, pedestal subtraction, a two-pass common mode correction and zero suppression in FPGA firmware. Moreover, the APV25 will be operated in multi-peak mode, where (typically) six samples along the shaped waveform are used for precise hit-time reconstruction which will also be implemented in FPGAs using look-up tables.
id cern-1235848
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
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spelling cern-12358482019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.417http://cds.cern.ch/record/1235848engFriedl, MIrmler, CPernicka, MReadout and Data Processing Electronics for the Belle-II Silicon Vertex DetectorDetectors and Experimental TechniquesA prototype readout system has been developed for the future Belle-II Silicon Vertex Detector at the Super-KEK-B factory in Tsukuba, Japan. It will receive raw data from double-sided sensors with a total of approximately 240,000 strips read out by APV25 chips at a trigger rate of up to 30kHz and perform strip reordering, pedestal subtraction, a two-pass common mode correction and zero suppression in FPGA firmware. Moreover, the APV25 will be operated in multi-peak mode, where (typically) six samples along the shaped waveform are used for precise hit-time reconstruction which will also be implemented in FPGAs using look-up tables.CERNoai:cds.cern.ch:12358482009
spellingShingle Detectors and Experimental Techniques
Friedl, M
Irmler, C
Pernicka, M
Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector
title Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector
title_full Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector
title_fullStr Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector
title_full_unstemmed Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector
title_short Readout and Data Processing Electronics for the Belle-II Silicon Vertex Detector
title_sort readout and data processing electronics for the belle-ii silicon vertex detector
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2009-006.417
http://cds.cern.ch/record/1235848
work_keys_str_mv AT friedlm readoutanddataprocessingelectronicsforthebelleiisiliconvertexdetector
AT irmlerc readoutanddataprocessingelectronicsforthebelleiisiliconvertexdetector
AT pernickam readoutanddataprocessingelectronicsforthebelleiisiliconvertexdetector

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