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Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC
The design and the preliminary measurements of a prototype 10 bit pipeline ADC based on 1.5-bit per stage architecture, developed for the luminosity detector at International Linear Collider (ILC) are presented. The ADC is designed in two versions, with and without a sample-and-hold circuit (S/H) at...
Autores principales: | , , |
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Lenguaje: | eng |
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CERN
2009
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.448 http://cds.cern.ch/record/1235855 |
_version_ | 1780918558531780608 |
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author | Idzik, Marek Swientek, Krzysztof Kulis, Szymon |
author_facet | Idzik, Marek Swientek, Krzysztof Kulis, Szymon |
author_sort | Idzik, Marek |
collection | CERN |
description | The design and the preliminary measurements of a prototype 10 bit pipeline ADC based on 1.5-bit per stage architecture, developed for the luminosity detector at International Linear Collider (ILC) are presented. The ADC is designed in two versions, with and without a sample-and-hold circuit (S/H) at the input. The prototypes are fabricated in 0.35 m CMOS technology. A dedicated test setup with a fast FPGA based data acquisition system (DAQ) is developed for the ADC testing. The measurements of static (INL, DNL) and dynamic parameters are performed to understand and quantify the circuit performance. The integral (INL) and differential (DNL) nonlinearity are below 1 LSB and 0.5 LSB respectively. The dynamic measurements show signal to noise (SNHR) ratio of about 58 dB for sampling frequency up to 25 MHz. |
id | cern-1235855 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2009 |
publisher | CERN |
record_format | invenio |
spelling | cern-12358552019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.448http://cds.cern.ch/record/1235855engIdzik, MarekSwientek, KrzysztofKulis, SzymonDesign and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILCDetectors and Experimental TechniquesThe design and the preliminary measurements of a prototype 10 bit pipeline ADC based on 1.5-bit per stage architecture, developed for the luminosity detector at International Linear Collider (ILC) are presented. The ADC is designed in two versions, with and without a sample-and-hold circuit (S/H) at the input. The prototypes are fabricated in 0.35 m CMOS technology. A dedicated test setup with a fast FPGA based data acquisition system (DAQ) is developed for the ADC testing. The measurements of static (INL, DNL) and dynamic parameters are performed to understand and quantify the circuit performance. The integral (INL) and differential (DNL) nonlinearity are below 1 LSB and 0.5 LSB respectively. The dynamic measurements show signal to noise (SNHR) ratio of about 58 dB for sampling frequency up to 25 MHz.CERNoai:cds.cern.ch:12358552009 |
spellingShingle | Detectors and Experimental Techniques Idzik, Marek Swientek, Krzysztof Kulis, Szymon Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC |
title | Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC |
title_full | Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC |
title_fullStr | Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC |
title_full_unstemmed | Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC |
title_short | Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC |
title_sort | design and measurements of 10 bit pipeline adc for the luminosity detector at ilc |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.5170/CERN-2009-006.448 http://cds.cern.ch/record/1235855 |
work_keys_str_mv | AT idzikmarek designandmeasurementsof10bitpipelineadcfortheluminositydetectoratilc AT swientekkrzysztof designandmeasurementsof10bitpipelineadcfortheluminositydetectoratilc AT kulisszymon designandmeasurementsof10bitpipelineadcfortheluminositydetectoratilc |