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A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process
This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was...
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| Lenguaje: | eng |
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CERN
2009
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| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.452 http://cds.cern.ch/record/1235856 |
| _version_ | 1780918558757224448 |
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| author | França-Santos, Hugo |
| author_facet | França-Santos, Hugo |
| author_sort | França-Santos, Hugo |
| collection | CERN |
| description | This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage. The power consumption is adjustable with the conversion rate and varies between 15 and 34mW for a 15 to 40MS/s conversion speed. The ADC occupies a silicon area of 0.7mm2 in a 0.13μm CMOS process and operates from a single 1.5V supply. |
| id | cern-1235856 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2009 |
| publisher | CERN |
| record_format | invenio |
| spelling | cern-12358562019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.452http://cds.cern.ch/record/1235856engFrança-Santos, HugoA 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS ProcessDetectors and Experimental TechniquesThis paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage. The power consumption is adjustable with the conversion rate and varies between 15 and 34mW for a 15 to 40MS/s conversion speed. The ADC occupies a silicon area of 0.7mm2 in a 0.13μm CMOS process and operates from a single 1.5V supply.CERNoai:cds.cern.ch:12358562009 |
| spellingShingle | Detectors and Experimental Techniques França-Santos, Hugo A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process |
| title | A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process |
| title_full | A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process |
| title_fullStr | A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process |
| title_full_unstemmed | A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process |
| title_short | A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process |
| title_sort | 10-bit 40ms/s pipelined adc in a 0.13μm cmos process |
| topic | Detectors and Experimental Techniques |
| url | https://dx.doi.org/10.5170/CERN-2009-006.452 http://cds.cern.ch/record/1235856 |
| work_keys_str_mv | AT francasantoshugo a10bit40msspipelinedadcina013mmcmosprocess AT francasantoshugo 10bit40msspipelinedadcina013mmcmosprocess |