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The Design of a High Speed Low Power Phase Locked Loop
The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25-μm Silicon-on- Sapphire (SoS) CMOS technology. Post-layout simulation indicates tha...
| Autores principales: | , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
CERN
2009
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.476 http://cds.cern.ch/record/1235862 |
| _version_ | 1780918559871860736 |
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| author | Liu, Tiankuan Gong, Datao Hou, Suen Liang, Zhihua Liu, Chonghan Su, Da-Shung Teng, Ping-Kun Xiang, Annie C Ye, Jingbo |
| author_facet | Liu, Tiankuan Gong, Datao Hou, Suen Liang, Zhihua Liu, Chonghan Su, Da-Shung Teng, Ping-Kun Xiang, Annie C Ye, Jingbo |
| author_sort | Liu, Tiankuan |
| collection | CERN |
| description | The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25-μm Silicon-on- Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79 – 5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented. |
| id | cern-1235862 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2009 |
| publisher | CERN |
| record_format | invenio |
| spelling | cern-12358622019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.476http://cds.cern.ch/record/1235862engLiu, TiankuanGong, DataoHou, SuenLiang, ZhihuaLiu, ChonghanSu, Da-ShungTeng, Ping-KunXiang, Annie CYe, JingboThe Design of a High Speed Low Power Phase Locked LoopDetectors and Experimental TechniquesThe upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25-μm Silicon-on- Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79 – 5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented.CERNoai:cds.cern.ch:12358622009 |
| spellingShingle | Detectors and Experimental Techniques Liu, Tiankuan Gong, Datao Hou, Suen Liang, Zhihua Liu, Chonghan Su, Da-Shung Teng, Ping-Kun Xiang, Annie C Ye, Jingbo The Design of a High Speed Low Power Phase Locked Loop |
| title | The Design of a High Speed Low Power Phase Locked Loop |
| title_full | The Design of a High Speed Low Power Phase Locked Loop |
| title_fullStr | The Design of a High Speed Low Power Phase Locked Loop |
| title_full_unstemmed | The Design of a High Speed Low Power Phase Locked Loop |
| title_short | The Design of a High Speed Low Power Phase Locked Loop |
| title_sort | design of a high speed low power phase locked loop |
| topic | Detectors and Experimental Techniques |
| url | https://dx.doi.org/10.5170/CERN-2009-006.476 http://cds.cern.ch/record/1235862 |
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