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Hardware studies for the upgrade of the ATLAS Central Trigger Processor

The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds as well as en...

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Detalles Bibliográficos
Autores principales: Berge, D, Burdalo, J, Ellis, N, Farthouat, P, Haas, S, Lundberg, J, Maettig, S, Messina, A, Pauly, T, Sherman, D, Spiwoks, R
Lenguaje:eng
Publicado: CERN 2009
Materias:
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.500
http://cds.cern.ch/record/1235872
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author Berge, D
Burdalo, J
Ellis, N
Farthouat, P
Haas, S
Lundberg, J
Maettig, S
Messina, A
Pauly, T
Sherman, D
Spiwoks, R
author_facet Berge, D
Burdalo, J
Ellis, N
Farthouat, P
Haas, S
Lundberg, J
Maettig, S
Messina, A
Pauly, T
Sherman, D
Spiwoks, R
author_sort Berge, D
collection CERN
description The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds as well as energy information received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to improve the rejection rate for the first phase of the luminosity upgrade of the LHC to 3∙1034 cm-2 s-1 planned for 2015, one of the options being studied consists of adding a topological trigger processor, using Region-Of-Interest information from the calorimeter and potentially also the muon trigger. This will require an upgrade of the CTP in order to accommodate the additional trigger inputs. The current CTP system consists of a 9U VME64x crate with 11 custom designed modules where the functionality is largely implemented in FPGAs. The constraint for the upgrade study presented here was to reuse the existing hardware as much as possible. This is achieved by operating the backplane at twice the design frequency and required developing new FPGA firmware for several of the CTP modules. We present the design of the newly developed firmware for the input, monitoring and core modules of the CTP as well as results from initial tests of the upgraded system.
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institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
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spelling cern-12358722019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.500http://cds.cern.ch/record/1235872engBerge, DBurdalo, JEllis, NFarthouat, PHaas, SLundberg, JMaettig, SMessina, APauly, TSherman, DSpiwoks, RHardware studies for the upgrade of the ATLAS Central Trigger ProcessorDetectors and Experimental TechniquesThe ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds as well as energy information received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to improve the rejection rate for the first phase of the luminosity upgrade of the LHC to 3∙1034 cm-2 s-1 planned for 2015, one of the options being studied consists of adding a topological trigger processor, using Region-Of-Interest information from the calorimeter and potentially also the muon trigger. This will require an upgrade of the CTP in order to accommodate the additional trigger inputs. The current CTP system consists of a 9U VME64x crate with 11 custom designed modules where the functionality is largely implemented in FPGAs. The constraint for the upgrade study presented here was to reuse the existing hardware as much as possible. This is achieved by operating the backplane at twice the design frequency and required developing new FPGA firmware for several of the CTP modules. We present the design of the newly developed firmware for the input, monitoring and core modules of the CTP as well as results from initial tests of the upgraded system.CERNoai:cds.cern.ch:12358722009
spellingShingle Detectors and Experimental Techniques
Berge, D
Burdalo, J
Ellis, N
Farthouat, P
Haas, S
Lundberg, J
Maettig, S
Messina, A
Pauly, T
Sherman, D
Spiwoks, R
Hardware studies for the upgrade of the ATLAS Central Trigger Processor
title Hardware studies for the upgrade of the ATLAS Central Trigger Processor
title_full Hardware studies for the upgrade of the ATLAS Central Trigger Processor
title_fullStr Hardware studies for the upgrade of the ATLAS Central Trigger Processor
title_full_unstemmed Hardware studies for the upgrade of the ATLAS Central Trigger Processor
title_short Hardware studies for the upgrade of the ATLAS Central Trigger Processor
title_sort hardware studies for the upgrade of the atlas central trigger processor
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.5170/CERN-2009-006.500
http://cds.cern.ch/record/1235872
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