FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links

The next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER)...

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Detalles Bibliográficos
Autores principales: Detraz, S, Silva, S, Moreira, P, Papadopoulos, S, Papakonstantinou, I, Seif El Nasr, S, Sigaud, C, Soos, C, Stejskal, P, Troska, J, Versmissen, H
Lenguaje:eng
Publicado: CERN 2009
Materias:
Engineering
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.636
http://cds.cern.ch/record/1236362
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author Detraz, S
Silva, S
Moreira, P
Papadopoulos, S
Papakonstantinou, I
Seif El Nasr, S
Sigaud, C
Soos, C
Stejskal, P
Troska, J
Versmissen, H
author_facet Detraz, S
Silva, S
Moreira, P
Papadopoulos, S
Papakonstantinou, I
Seif El Nasr, S
Sigaud, C
Soos, C
Stejskal, P
Troska, J
Versmissen, H
author_sort Detraz, S
collection CERN
description The next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in a Xilinx Virtex-5 FPGA device and discusses the experimental results.
id cern-1236362
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2009
publisher CERN
record_format invenio
spelling cern-12363622019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.636http://cds.cern.ch/record/1236362engDetraz, SSilva, SMoreira, PPapadopoulos, SPapakonstantinou, ISeif El Nasr, SSigaud, CSoos, CStejskal, PTroska, JVersmissen, HFPGA-based Bit-Error-Rate Tester for SEU-hardened Optical LinksEngineeringThe next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in a Xilinx Virtex-5 FPGA device and discusses the experimental results.CERNoai:cds.cern.ch:12363622009
spellingShingle Engineering
Detraz, S
Silva, S
Moreira, P
Papadopoulos, S
Papakonstantinou, I
Seif El Nasr, S
Sigaud, C
Soos, C
Stejskal, P
Troska, J
Versmissen, H
FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links
title FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links
title_full FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links
title_fullStr FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links
title_full_unstemmed FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links
title_short FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links
title_sort fpga-based bit-error-rate tester for seu-hardened optical links
topic Engineering
url https://dx.doi.org/10.5170/CERN-2009-006.636
http://cds.cern.ch/record/1236362
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