The Design and Implementation in $0.13\mu m$ CMOS of an Algorithm Permitting Spectroscopic Imaging with High Spatial Resolution for Hybrid Pixel Detectors

Advances in pixel detector technology are opening up new possibilities in many fields of science. Modern High Energy Physics (HEP) experiments use pixel detectors in tracking systems where excellent spatial resolution, precise timing and high signal-to-noise ratio are required for accurate and clean track reconstruction. Many groups are working worldwide to adapt the hybrid pixel technology to other fields such as medical X-ray radiography, protein structure analysis or neutron imaging. The Medipix3 chip is a 256x256 channel hybrid pixel detector readout chip working in Single Photon Counting Mode. It has been developed with a new front-end architecture aimed at eliminating the spectral distortion produced by charge diffusion in highly segmented semiconductor detectors. In the new architecture neighbouring pixels communicate with one another. Charges can be summed event-by-event and the incoming quantum can be assigned as a single hit to the pixel with the biggest charge deposit. In the case where incoming X-ray photons produce fluorescence – a particular issue in high-Z materials – the charge deposited by those fluorescent photons will be included in the charge sum provided that the deposition takes place within the volume of the pixels neighbouring the initial impact point. The chip is configurable such that either the dimensions of each detector pixel match those of one readout pixel or detector pixels are 4 times greate r in area than the readout pixels. In the latter case event-by-event summing is still possible between the larger pixels. The pixel cell occupies an area of $55\mu m x 55\mu m$. It contains an analog front-end and digital processing circuitry. The analog front end consists of a preamplifier, a shaper and two threshold discriminators. The first discriminator is used to define the lower threshold and as input to the arbitration logic when charge summing is enabled. The second discriminator can be used to define a second threshold. Clusters of 4 pixels can be grouped in a single detection unit allowing up to 8 thresholds for energy binning. The digital circuitry contains control logic, arbitration modules for hit allocation, circuitry for storage of the pixel configuration data and two registers that can be configured as two 1-bit, 4-bit or 12 bit counters or as a single 24 bit counter. In 24-bit counting mode only one discrimination level is used and DAQ(write) and readout(read) are sequential. With lower counter depths it is possible to have 2 discrimination levels per pixel in sequential read/write or a single threshold per pixel in continuous read/write. The chip was designed and manufactured in an 8-metal $0.13\mu m$ CMOS technology. It contains ~115M transistors. Measurements show an Equivalent Noise Charge of ~70e- rms (Single Pixel Mode) and ~140e- rms (Charge Summing Mode).