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Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility
| Autores principales: | , , , , |
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| Lenguaje: | eng |
| Publicado: |
1981
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1109/TC.1981.1675830 http://cds.cern.ch/record/126866 |
| _version_ | 1780879295793594368 |
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| author | Van Dam, A Barbacci, M R Halatsis, C Joosten, J Letheren, M F |
| author_facet | Van Dam, A Barbacci, M R Halatsis, C Joosten, J Letheren, M F |
| author_sort | Van Dam, A |
| collection | CERN |
| id | cern-126866 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 1981 |
| record_format | invenio |
| spelling | cern-1268662019-09-30T06:29:59Zdoi:10.1109/TC.1981.1675830http://cds.cern.ch/record/126866engVan Dam, ABarbacci, M RHalatsis, CJoosten, JLetheren, M FSimulation of a horizontal bit-sliced processor using the ISPS architecture simulation facilityDetectors and Experimental TechniquesCERN-DD-80-30oai:cds.cern.ch:1268661981 |
| spellingShingle | Detectors and Experimental Techniques Van Dam, A Barbacci, M R Halatsis, C Joosten, J Letheren, M F Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility |
| title | Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility |
| title_full | Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility |
| title_fullStr | Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility |
| title_full_unstemmed | Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility |
| title_short | Simulation of a horizontal bit-sliced processor using the ISPS architecture simulation facility |
| title_sort | simulation of a horizontal bit-sliced processor using the isps architecture simulation facility |
| topic | Detectors and Experimental Techniques |
| url | https://dx.doi.org/10.1109/TC.1981.1675830 http://cds.cern.ch/record/126866 |
| work_keys_str_mv | AT vandama simulationofahorizontalbitslicedprocessorusingtheispsarchitecturesimulationfacility AT barbaccimr simulationofahorizontalbitslicedprocessorusingtheispsarchitecturesimulationfacility AT halatsisc simulationofahorizontalbitslicedprocessorusingtheispsarchitecturesimulationfacility AT joostenj simulationofahorizontalbitslicedprocessorusingtheispsarchitecturesimulationfacility AT letherenmf simulationofahorizontalbitslicedprocessorusingtheispsarchitecturesimulationfacility |