Development of a new Silicon Tracker at CMS for Super-LHC

Tracking is an essential requirement for any high energy particle physics experiment. The Compact Muon Solenoid (CMS) detector at the Large Hadron Collider (LHC) employs an all silicon tracker, the largest of its kind, for the precise measurement of track momentum and vertex position. With approximately 10 million detector channels in the strip tracker alone, the analogue non-sparsified readout system has been designed to handle the large data volumes generated at the 100 kHz Level 1 (L1) trigger rate. Fluctuations in the event rate are controlled using buffers whose occupancies are constantly monitored to prevent overflows, otherwise causing loss of synchronisation and data. The status of the tracker is reported by the APV emulator (APVe), which has now been successfully commissioned within the silicon strip tracker readout system. The APVe plays a crucial role in the synchronisation of the tracker by deterministic calculation of the front end buffer occupancy and by monitoring the status of the Front End Drivers (FEDs), where the tracker data is received and processed. In the event that the buffers are close to overflow, the APVe is required to veto L1 triggers until the system is ready. As such, it is important that APVe is correctly implemented so that the tracker can operate with minimal dead time. The integration of the APVe with the tracker readout and trigger control systems is discussed and the steps taken to en sure its correct operation are presented. The Super-LHC is a proposed LHC machine upgrade to increase the luminosity by a factor of 10. The increased particle fluxes and radiation environment will necessitate the complete replacement of the current CMS tracker while presenting the design of a new tracker with severe challenges. Power consumption is one of the main challenges for the tracker readout system since a higher granularity detector will be required. Physics performance must not be compromised so the tracker material contribution should be lowered where possible. In addition, it is likely that the Level 1 system will require information from the tracker in order to reduce the trigger rate. A method of reducing the on-detector data rate for input into a L1 trigger using closely separated pixel layers is presented. A detailed simulation of a concept tracker geometry has been developed and the triggering performance has been estimated. The simulations report that the presented tracking trigger layer would be viable for use at SLHC. A layer would be capable of reducing the detector data rate by a factor of ~20 while maintaining efficiencies in excess of 96% for tracks with pT<2 GeV/c. The information provided by a single stacked layer would not be useful for reducing the L1 trigger rate, but two stacked layers are able to reconstruct tracks with dpT/pT<20% for pT<20 GeV/c and with sufficient resolution so as to match tracks with L1 calorimeter objects.