The ATLAS Insertable B-Layer Detector (IBL)

The upgrade for the ATLAS detector will undergo different phases towards SLHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during a longer shutdown of the LHC machine, the so-called Phase I Upgrade. The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of about 3.2 cm. The IBL requires the development of several new technologies to cope with the increase of radiation and pixel occupancy as well as to improve the physics performance of the existing pixel detector. In order to achieve these goals the pixel size is reduced and the material budget is minimized by using new lightweight mechanical support materials and a CO2 based cooling system. Main component of the module development for the IBL is the new ATLAS pixel readout chip, FE-I4, designed in 130 nm technology which features an array of 80 by 336 pixels with a pixel size of 50x250 µm2. Because of the increased pixel occupancy the digital readout concept has been completely redesigned now using a 4 pixel region which stores the hit information until the L1 trigger decision is taken. Regarding the pixel sensors three different promising sensor technologies are currently under investigation. These are planar n-on-n or n-on-p silicon sensors, full 3D silicon sensors with active edges and pixel sensors mad e off polycrystalline CVD diamonds. All sensor candidates promise high radiation tolerance together with a minimal inactive area to allow efficient module placement. The challenge for the mechanics is the construction of lightweight and robust support and cooling structures which have to fit in the limited space between the beam pipe and the existing pixel detector and need to be inserted with high precision into the complex environment of the ATLAS Inner Detector. An overview of the project with particular emphasis on the IBL layout, specifications, performance and module development including hybridization technologies is presented.