ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels

An additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed...

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Detalles Bibliográficos
Autores principales: Gabrielli, A, Bruni, G, Bruschi, M, D’Antone, I, Dopke, J, Falchieri, D, Flick, T, Gross-Kettner, J, Joseph, J, Krieger, N, Kugel, A, Morettini, P, Polini, A, Rizzi, M, Christian Schroer, N, Travaglini, R, Zannoli, S, Zoccoli, A
Lenguaje:eng
Publicado: 2010
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1292295
Descripción
Sumario:An additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS DAQ system.

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