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ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels
An additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed...
Autores principales: | , , , , , , , , , , , , , , , , , |
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Lenguaje: | eng |
Publicado: |
2010
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1292295 |
_version_ | 1780920759978295296 |
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author | Gabrielli, A Bruni, G Bruschi, M D’Antone, I Dopke, J Falchieri, D Flick, T Gross-Kettner, J Joseph, J Krieger, N Kugel, A Morettini, P Polini, A Rizzi, M Christian Schroer, N Travaglini, R Zannoli, S Zoccoli, A |
author_facet | Gabrielli, A Bruni, G Bruschi, M D’Antone, I Dopke, J Falchieri, D Flick, T Gross-Kettner, J Joseph, J Krieger, N Kugel, A Morettini, P Polini, A Rizzi, M Christian Schroer, N Travaglini, R Zannoli, S Zoccoli, A |
author_sort | Gabrielli, A |
collection | CERN |
description | An additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS DAQ system. |
id | cern-1292295 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2010 |
record_format | invenio |
spelling | cern-12922952019-09-30T06:29:59Zhttp://cds.cern.ch/record/1292295engGabrielli, ABruni, GBruschi, MD’Antone, IDopke, JFalchieri, DFlick, TGross-Kettner, JJoseph, JKrieger, NKugel, AMorettini, PPolini, ARizzi, MChristian Schroer, NTravaglini, RZannoli, SZoccoli, AATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixelsDetectors and Experimental TechniquesAn additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS DAQ system.ATL-INDET-SLIDE-2010-300oai:cds.cern.ch:12922952010-09-17 |
spellingShingle | Detectors and Experimental Techniques Gabrielli, A Bruni, G Bruschi, M D’Antone, I Dopke, J Falchieri, D Flick, T Gross-Kettner, J Joseph, J Krieger, N Kugel, A Morettini, P Polini, A Rizzi, M Christian Schroer, N Travaglini, R Zannoli, S Zoccoli, A ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels |
title | ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels |
title_full | ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels |
title_fullStr | ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels |
title_full_unstemmed | ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels |
title_short | ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels |
title_sort | atlas ibl: integration of new hw/sw readout features for the additional layer of pixels |
topic | Detectors and Experimental Techniques |
url | http://cds.cern.ch/record/1292295 |
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