ATLAS IBL: Integration of new HW/SW readout features for the additional layer of Pixel Detector

An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FeI4, which requires new off-detector electronics, currently realized with two VME-based boards, which implement optical I/O...

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Detalles Bibliográficos
Autores principales: Bruni, G, Bruschi, M, D’Antone, I, Dopke, J, Falchieri, D, Flick, T, Gabrielli, A, Gross-Kettner, J, Joseph, J, Krieger, N, Kugel, A, Morettini, P, Polini, A, Rizzi, M, Schroer, N C, Travaglini, R, Zannoli, S, Zoccoli, A
Lenguaje:eng
Publicado: 2010
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/6/01/C01018
http://cds.cern.ch/record/1301775
Descripción
Sumario:An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FeI4, which requires new off-detector electronics, currently realized with two VME-based boards, which implement optical I/O functionality (BOC card) and data processing functionality (ROD card), plus a timing interface module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board.

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