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Digital VLSI chip design with Cadence and Synopsys CAD tools
| Autor principal: | |
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| Lenguaje: | eng |
| Publicado: |
Addison-Wesley
2010
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1331882 |
| _version_ | 1780921754869301248 |
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| author | Brunvand, Erik |
| author_facet | Brunvand, Erik |
| author_sort | Brunvand, Erik |
| collection | CERN |
| id | cern-1331882 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2010 |
| publisher | Addison-Wesley |
| record_format | invenio |
| spelling | cern-13318822021-04-22T01:07:51Zhttp://cds.cern.ch/record/1331882engBrunvand, ErikDigital VLSI chip design with Cadence and Synopsys CAD toolsEngineeringAddison-Wesleyoai:cds.cern.ch:13318822010 |
| spellingShingle | Engineering Brunvand, Erik Digital VLSI chip design with Cadence and Synopsys CAD tools |
| title | Digital VLSI chip design with Cadence and Synopsys CAD tools |
| title_full | Digital VLSI chip design with Cadence and Synopsys CAD tools |
| title_fullStr | Digital VLSI chip design with Cadence and Synopsys CAD tools |
| title_full_unstemmed | Digital VLSI chip design with Cadence and Synopsys CAD tools |
| title_short | Digital VLSI chip design with Cadence and Synopsys CAD tools |
| title_sort | digital vlsi chip design with cadence and synopsys cad tools |
| topic | Engineering |
| url | http://cds.cern.ch/record/1331882 |
| work_keys_str_mv | AT brunvanderik digitalvlsichipdesignwithcadenceandsynopsyscadtools |