Cargando…

ATLAS calorimeter and topological trigger upgrades for Phase 1

The ATLAS Level-1 Calorimeter Trigger (L1Calo) collaboration is pursuing two hardware upgrade programs for Phase 1 of the LHC upgrade. The first of these is development of a new mixed-signal multi-chip module (MCM) for the PreProcessor system. based on faster FADCs and a modern FPGA. Designed as a d...

Descripción completa

Detalles Bibliográficos
Autor principal: Silverstein, S
Lenguaje:eng
Publicado: 2011
Materias:
Acceso en línea:http://cds.cern.ch/record/1335684
_version_ 1780921807966044160
author Silverstein, S
author_facet Silverstein, S
author_sort Silverstein, S
collection CERN
description The ATLAS Level-1 Calorimeter Trigger (L1Calo) collaboration is pursuing two hardware upgrade programs for Phase 1 of the LHC upgrade. The first of these is development of a new mixed-signal multi-chip module (MCM) for the PreProcessor system. based on faster FADCs and a modern FPGA. Designed as a drop-in replacement for the existing MCM, the FPGA also enables future upgrades to the PreProcessor algorithms, including enhanced digital filtering and compensation for time-variation of pedestals. It is also planned to augment the current multiplicity-based trigger by adding topology-based algorithms. This is made possible by adding jet and EM/hadron Regions of Interest (ROIs) to the L1Calo real time data path. A synchronous, pipelined topological processor (TP) based on high-density FPGAs and multi-Gbit optical links gathers all ROI information and performs topological algorithms.
id cern-1335684
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2011
record_format invenio
spelling cern-13356842019-09-30T06:29:59Zhttp://cds.cern.ch/record/1335684engSilverstein, SATLAS calorimeter and topological trigger upgrades for Phase 1Detectors and Experimental TechniquesThe ATLAS Level-1 Calorimeter Trigger (L1Calo) collaboration is pursuing two hardware upgrade programs for Phase 1 of the LHC upgrade. The first of these is development of a new mixed-signal multi-chip module (MCM) for the PreProcessor system. based on faster FADCs and a modern FPGA. Designed as a drop-in replacement for the existing MCM, the FPGA also enables future upgrades to the PreProcessor algorithms, including enhanced digital filtering and compensation for time-variation of pedestals. It is also planned to augment the current multiplicity-based trigger by adding topology-based algorithms. This is made possible by adding jet and EM/hadron Regions of Interest (ROIs) to the L1Calo real time data path. A synchronous, pipelined topological processor (TP) based on high-density FPGAs and multi-Gbit optical links gathers all ROI information and performs topological algorithms.ATL-DAQ-SLIDE-2011-089oai:cds.cern.ch:13356842011-03-14
spellingShingle Detectors and Experimental Techniques
Silverstein, S
ATLAS calorimeter and topological trigger upgrades for Phase 1
title ATLAS calorimeter and topological trigger upgrades for Phase 1
title_full ATLAS calorimeter and topological trigger upgrades for Phase 1
title_fullStr ATLAS calorimeter and topological trigger upgrades for Phase 1
title_full_unstemmed ATLAS calorimeter and topological trigger upgrades for Phase 1
title_short ATLAS calorimeter and topological trigger upgrades for Phase 1
title_sort atlas calorimeter and topological trigger upgrades for phase 1
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1335684
work_keys_str_mv AT silversteins atlascalorimeterandtopologicaltriggerupgradesforphase1