Cyfrowy synchroniczny układ ASIC, jako detektor promieniowania neutronowego

The paper presents a design of neutron radiation detector. The neutron detector was designed with the application of sensitive to reversible Single Event Upsets (SEUs) digital circuit. The detector bases on a modified shift register (see fig. 3), using dual supply voltage.. The paper presents a number of methods that were developed to enhance sensitivity of the detector to reversible SEUs. The paper discuses physical phenomena that have influenced on the technological fabrication process and topology of the integrated circuit. Some exemplary parameters of the designed register has been given (input capacitance, clock-to-output delay) for the internal flip-flops, pre-layout, as well as post-layout (with extracted parasitic components) simulations, with visible (e.g. approx. 2-3 times) difference between ideal (pre-layout) and real (post-layout) design. The simulation tests and the final layout (see fig. 4) were prepared using CADENCE IC environment in 6.1.4 version, as the process design kit for chosen ITE CMOS technology allowed. General research background and realization perspective (selected foundry run) was shown in the conclusion chapter. Also the perspectives of a future testbench circuit in real and factual radiation environment were briefly described.