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The Fast Tracker Real Time Processor: high quality real-time tracking at ATLAS
As the LHC luminosity is ramped up to the design level of 1x1034 cm−2 s−1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reducti...
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Lenguaje: | eng |
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2011
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/1371006 |
Sumario: | As the LHC luminosity is ramped up to the design level of 1x1034 cm−2 s−1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the most important physics and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK)[1], [2] is a proposed upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK is a dedicated Super Computer based on a mixture of advanced technologies. The architecture broadly employs powerful Field Programmable Gate Arrays (FPGAs), the modern programmable devices, but the greatest computing power is provided by ASICs named Associative Memories (AM), containing full-custom CAM cells. FTK solves the combinatorial challenge inherent to tracking by exploiting massive parallelism of the AM so that inner detector hits can be compared to millions of pre-calculated patterns simultaneously. Pattern recognition is complete by the time the data are loaded into the devices. Track fitting within matched patterns is simplified by using pre-computed linearized fitting constants and leveraging fast DSPs in modern commercial FPGAs. Overall, FTK is able to compute the helix parameters for all tracks in an event and apply quality cuts in less than 100 microseconds. We present the architecture, the performance and the technical challenges of the boards and the ASIC in the project. [1] IEEE Trans. Nucl. Sci. 48, 575 (2001) [2] IEEE Trans. Nucl. Sci. 51, 391 (2004) |
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